this paper presents the first mm-Wave PLL utilizing a subsampling phase detector instead of a classical divider chain. Implemented in 40nm CMOS, the PLL has a jitter as low as 230fs for a power consumption of 42mW.
Szortyka, V, Shi, Q, Raczkowski, K, Parvais, B, Kuijk, M & Wambacq, P 2014, A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS. in 2014 IEEE International Solid-State Circuits Conference. 2014 IEEE International Solid-State Circuits Conference, pp. 105-108, 2014 IEEE International Solid-State Circuits Conference, ISSCC, San Francisco, CA, United States, 9/02/14.
Szortyka, V., Shi, Q., Raczkowski, K., Parvais, B., Kuijk, M., & Wambacq, P. (2014). A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS. In 2014 IEEE International Solid-State Circuits Conference (pp. 105-108). (2014 IEEE International Solid-State Circuits Conference).
@inproceedings{769ff136f58349b2ad5b5855ba8b2f87,
title = "A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS",
abstract = "this paper presents the first mm-Wave PLL utilizing a subsampling phase detector instead of a classical divider chain. Implemented in 40nm CMOS, the PLL has a jitter as low as 230fs for a power consumption of 42mW.",
keywords = "CMOS, PLL, sub-sampling, mm-wave",
author = "Viki Szortyka and Qixian Shi and Kuba Raczkowski and Bertrand Parvais and Maarten Kuijk and Piet Wambacq",
year = "2014",
month = feb,
day = "13",
language = "English",
isbn = "978-1-4799-0920-9",
series = "2014 IEEE International Solid-State Circuits Conference",
pages = "105--108",
booktitle = "2014 IEEE International Solid-State Circuits Conference",
note = "2014 IEEE International Solid-State Circuits Conference, ISSCC ; Conference date: 09-02-2014 Through 13-02-2014",
}