Spagnolo, A., Verbruggen, B., D'amico, S., & Wambacq, P. (2014). A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS. In European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th (pp. 75-78). IEEE. https://doi.org/10.1109/ESSCIRC.2014.6942025

@inproceedings{bb6fcc85323e4f4b833ceee06e844378,
title = "A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS",
abstract = "A 7b time interleaved hybrid ADC in 40nm CMOS is presented. The ADC consists of two pipelined stages and combines an intrinsically linear SAR with a fully calibrated binary search architecture to achieve energy efficiency. The first stage of each channel consists of a 3b SAR followed by a dynamic amplifier merged with a comparator. The second stage is a 3b comparator-based asynchronous binary search with threshold calibration to compensate amplifier nonlinearity. The calibration references are generated on chip by using the DAC embedded in the first stage. The prototype achieves a peak SNDR of 38dB at 3.5GS/s while consuming approximately 6.2mW.",
author = "Annachiara Spagnolo and Bob Verbruggen and Stefano D'amico and Piet Wambacq",
year = "2014",
doi = "10.1109/ESSCIRC.2014.6942025",
language = "English",
isbn = "978-1-4799-5694-4",
pages = "75--78",
booktitle = "European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th",
publisher = "IEEE",
note = "European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 ; Conference date: 22-09-2014 Through 26-09-2014",
}