Verbruggen, B., Deguchi, K., Malki, B., & Craninckx, J. (2014). A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS. In VLSI Circuits Digest of Technical Papers, 2014 Symposium on (pp. 1-2). IEEE. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6858451

@inproceedings{251b77db88d74b1ea78d9330e594f1a6,
title = "A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS",
abstract = "We present a 200 MS/s 2x interleaved 14 bit pipelined SAR ADC in 28nm digital CMOS. The ADC uses a new residue amplifier for low noise at low power, and incorporates interleaved channel time-constant calibration. The ADC achieves a peak SNDR of 70.7 dB at 200 MS/s while consuming 2.3 mW from an 0.9 V supply.",
keywords = "CMOS digital integrated circuits amplifiers analog",
author = "Bob Verbruggen and Kazuaki Deguchi and Badr Malki and J. Craninckx",
year = "2014",
month = jun,
day = "13",
language = "English",
isbn = "978-1-4799-3327-3",
pages = "1--2",
booktitle = "VLSI Circuits Digest of Technical Papers, 2014 Symposium on",
publisher = "IEEE",
note = "2014 Symposium on VLSI Circuits ; Conference date: 10-06-2014 Through 13-06-2014",
}