Raczkowski, K., Markulic, N., Hershberg, B., Van Driessche, J., & Craninckx, J. (2014). A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter. In 2014 IEEE Radio Frequency Integrated Circuits Symposium (pp. 89-92). IEEE.

@inproceedings{c112de14fae345908805692680518c47,
title = "A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter",
abstract = "This paper describes a fractional-N subsampling PLL in 28nm CMOS. Fractional lock is achieved by using a 10bit digital-to-time converter (DTC) that generates a delayed sampling clock with minimal impact on PLL performance. Background calibration guarantees appropriate DTC gain, reducing spurs. The system achieves -38 dBc of integrated phase noise (280fs RMS jitter) at 10GHz when a worst-case fractional spur of -43 dBc is present. In-band phase noise is at the level of -104 dBc/Hz. The class-B VCO used can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9V and 1.8V supplies.",
author = "Kuba Raczkowski and Nereo Markulic and Benjamin Hershberg and {Van Driessche}, Joris and Jan Craninckx",
year = "2014",
language = "English",
isbn = "978-1-4799-3862-9",
pages = "89--92",
booktitle = "2014 IEEE Radio Frequency Integrated Circuits Symposium",
publisher = "IEEE",
note = "2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) ; Conference date: 01-06-2014 Through 03-06-2014",
}