Malki, B., Verbruggen, B., Wambacq, P., Deguchi, K., Iriguchi, M., & Craninckx, J. (2014). A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC. In ESSCIRC 2014 - 40th European Solid State Circuits Conference (pp. 215-218). (Proceedings of European Solid State Circuits Conference (ESSCIRC); Vol. 40). IEEE. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6942060

@inproceedings{307af74bcd354517ab2fb811c9743d24,
title = "A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC",
abstract = "A complementary dynamic single-stage residue amplifier for a pipelined SAR ADC is presented. It re-uses charge typically wasted during the reset phase, and hence improves efficiency by a factor 2× in this block that often dominates the fundamental noise/power trade-off of the ADC. The residue amplifier achieves 90 µVrms input noise for an energy consumption of 1.5 pJ. It is used in a 2-times interleaved 6b coarse/8b fine pipelined SAR ADC. The 40nm CMOS prototype achieves 11 ENOB at 20 MS/s while consuming 165 µW, leading to an energy per conversion step of 4 fJ. It maintains more than 10.8 ENOB at low input frequencies for a clock frequency up to 180 MS/s.",
keywords = "CMOS 40nm Common mode detector Pipelined SAR ADC S",
author = "Badr Malki and Bob Verbruggen and Piet Wambacq and Kazuaki Deguchi and Masao Iriguchi and J. Craninckx",
year = "2014",
month = sep,
day = "26",
language = "English",
isbn = "978-1-4799-5694-4",
series = "Proceedings of European Solid State Circuits Conference (ESSCIRC)",
publisher = "IEEE",
pages = "215--218",
booktitle = "ESSCIRC 2014 - 40th European Solid State Circuits Conference",
note = "40th European Solid-State Circuits Conference ; Conference date: 22-09-2014 Through 26-09-2014",
}