Ryckaert, J., Raghavan, P., Baert, R., Bardon, M. G., Dusa, M., Mallik, A., Sakhare, S., Vandewalle, B., Wambacq, P., Chava, B., Croes, K., Dehan, M., Jang, D., Leray, P., Liu, T.-T., Miyaguchi, K., Parvais, B., Schuddinck, P., Weemaes, P., ... Steegen, A. (2014). Design Technology co-optimization for N10. In IEEE 2014 Custom Integrated Circuits Conference (pp. 1-8). IEEE. https://doi.org/10.1109/CICC.2014.6946037

@inproceedings{a91c74b18e7740028d19fad958c03e2d,
title = "Design Technology co-optimization for N10",
abstract = "Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.",
author = "Julien Ryckaert and Praveen Raghavan and R Baert and Bardon, {M Garcia} and M. Dusa and A. Mallik and Sushil Sakhare and B. Vandewalle and Piet Wambacq and B. Chava and K. Croes and M. Dehan and D. Jang and P. Leray and T.-T. Liu and Kenichi Miyaguchi and Bertrand Parvais and P. Schuddinck and P. Weemaes and A. Mercha and J. B{\"o}mmels and N. Horiguchi and G. McIntyre and Aaron Thean and Z Tokei and S. Cheng and Diederik Verkest and A. Steegen",
year = "2014",
doi = "10.1109/CICC.2014.6946037",
language = "English",
pages = "1--8",
booktitle = "IEEE 2014 Custom Integrated Circuits Conference",
publisher = "IEEE",
note = "IEEE 2014 Custom Integrated Circuits Conference, CICC 2014 ; Conference date: 15-09-2014 Through 17-09-2014",
url = "https://www.ieee.org/conferences_events/conferences/conferencedetails/index.html?Conf_ID=18693",
}