Verbruggen, A., Iriguchi, M., De La Guia Solaz, M., Glorieux, G., Deguchi, K., Malki, B., & Craninckx, J. (2013). A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS. In IEEE VLSI Symposium Circuits (pp. 268-269). (IEEE VLSI Symposium Circuits). http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6578690

@inbook{c427dcb6b2d541a794c531d0fc115b9d,
title = "A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS",
abstract = "A 410 MS/s 2x interleaved 11bit pipelined SAR ADC in 28nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR and includes an on-chip calibration engine that detects and corrects comparator offsets and amplifier gain errors in the background. The ADC achieves a peak SNDR of 59.8 dB at 410 MS/s for an energy per conversion step of 6.5 fJ.",
keywords = "pipelined SAR, calibration",
author = "A. Verbruggen and Masao Iriguchi and {De La Guia Solaz}, Manuel and Guy Glorieux and Kazuaki Deguchi and Badr Malki and J. Craninckx",
year = "2013",
month = jun,
day = "12",
language = "English",
isbn = "978-1-4673-5531-5",
series = "IEEE VLSI Symposium Circuits",
pages = "268--269",
booktitle = "IEEE VLSI Symposium Circuits",
}