Abstract:This paper reviews some important process aspects of aggressively downscaled FinFET technologies and their implications on digital and analog figures of merits (FOMs). The need to downscale device architectures to enhance digital transistor electrostatics and circuit density led to influences in parasitics, variability, and noise, which impact analog FOMs. Therefore, it is important to understand the trade-offs due to the new devices and the upcoming process solutions to address them. Process features, variability and parasitics relevant to 14nm and beyond FinFET will be reviewed and their System-On-Chip (SOC) implications will be discussed.
Thean, A, Wambacq, P, Lee, J, Cho, M, Veloso, A, Sasaki, Y, Chiarella, T, Miyaguchi, K, Parvais, B, Bardon, MG, Schuddinck, P, Kim, M, Horiguchi, N, Dehan, M, Mercha, A, Van Der Plas, G, Collaert, N & Verkest, D 2013, Impact of multi-gate device architectures on digital and analog circuits and its implications on system-on-chip technologies. in 2013 IEEE International Electron Devices Meeting (IEDM). IEEE, pp. 448-451, 2013 IEEE International Electron Devices Meeting , Washington, United States, 9/12/13. https://doi.org/10.1109/IEDM.2013.6724647
Thean, A., Wambacq, P., Lee, J., Cho, M., Veloso, A., Sasaki, Y., Chiarella, T., Miyaguchi, K., Parvais, B., Bardon, M. G., Schuddinck, P., Kim, M., Horiguchi, N., Dehan, M., Mercha, A., Van Der Plas, G., Collaert, N., & Verkest, D. (2013). Impact of multi-gate device architectures on digital and analog circuits and its implications on system-on-chip technologies. In 2013 IEEE International Electron Devices Meeting (IEDM) (pp. 448-451). IEEE. https://doi.org/10.1109/IEDM.2013.6724647
@inproceedings{fa2e1697d6d44e99a41fea95dfb21aad,
title = "Impact of multi-gate device architectures on digital and analog circuits and its implications on system-on-chip technologies",
abstract = "Abstract:This paper reviews some important process aspects of aggressively downscaled FinFET technologies and their implications on digital and analog figures of merits (FOMs). The need to downscale device architectures to enhance digital transistor electrostatics and circuit density led to influences in parasitics, variability, and noise, which impact analog FOMs. Therefore, it is important to understand the trade-offs due to the new devices and the upcoming process solutions to address them. Process features, variability and parasitics relevant to 14nm and beyond FinFET will be reviewed and their System-On-Chip (SOC) implications will be discussed.",
author = "Aaron Thean and Piet Wambacq and J. Lee and M. Cho and A Veloso and Y. Sasaki and T. Chiarella and Kenichi Miyaguchi and Bertrand Parvais and Bardon, {M Garcia} and P. Schuddinck and M. Kim and N. Horiguchi and M. Dehan and A. Mercha and {Van Der Plas}, Geert and Nadine Collaert and Diederik Verkest",
year = "2013",
doi = "10.1109/IEDM.2013.6724647",
language = "English",
pages = "448--451",
booktitle = "2013 IEEE International Electron Devices Meeting (IEDM)",
publisher = "IEEE",
note = "2013 IEEE International Electron Devices Meeting , IEDM ; Conference date: 09-12-2013 Through 11-12-2013",
url = "http://www.ieee.org/conferences_events/conferences/conferencedetails/index.htm?Conf_ID=11125",
}