Julien Ryckaert, Jonathan Borremans, Bob Verbruggen, Lynn Bos, Costantino Armiento, J. Craninckx, G. Van Der Plas
A sixth-order RF bandpass DeltaSigma ADC operating on the 2.4 GHz ISM band, which is suitable for RF digitization is presented. The bandpass loop filter is based on digitally programmable Gm-LC resonators that can be calibrated online to adjust the RF center frequency. By sampling below the input Nyquist frequency, the clock in the system was reduced to 3 GHz, allowing a large reduction of the power consumption. Implemented in a standard 90 nm CMOS process, the IC achieves 40 dB and 62 dB of SNDR and SFDR, respectively, on a 60 MHz bandwidth with 40 mW of power consumption leading to a FoM of 245 GHz/W (4.1 pJ/conversion step). This implementation paves a possible way towards direct RF digitization receiver architectures.
Ryckaert, J, Borremans, J, Verbruggen, B, Bos, L, Armiento, C, Craninckx, J & Van Der Plas, G 2009, 'A 2.4 GHz Low-Power Sixth-Order RF Bandpass Delta Sigma Converter in CMOS', IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 44, pp. 2873-2880.
Ryckaert, J., Borremans, J., Verbruggen, B., Bos, L., Armiento, C., Craninckx, J., & Van Der Plas, G. (2009). A 2.4 GHz Low-Power Sixth-Order RF Bandpass Delta Sigma Converter in CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 44, 2873-2880.
@article{34ab5cabf17849f79bc25a75b0f68d6e,
title = "A 2.4 GHz Low-Power Sixth-Order RF Bandpass Delta Sigma Converter in CMOS",
abstract = "A sixth-order RF bandpass DeltaSigma ADC operating on the 2.4 GHz ISM band, which is suitable for RF digitization is presented. The bandpass loop filter is based on digitally programmable Gm-LC resonators that can be calibrated online to adjust the RF center frequency. By sampling below the input Nyquist frequency, the clock in the system was reduced to 3 GHz, allowing a large reduction of the power consumption. Implemented in a standard 90 nm CMOS process, the IC achieves 40 dB and 62 dB of SNDR and SFDR, respectively, on a 60 MHz bandwidth with 40 mW of power consumption leading to a FoM of 245 GHz/W (4.1 pJ/conversion step). This implementation paves a possible way towards direct RF digitization receiver architectures.",
keywords = "GHz Low-Power",
author = "Julien Ryckaert and Jonathan Borremans and Bob Verbruggen and Lynn Bos and Costantino Armiento and J. Craninckx and {Van Der Plas}, G.",
year = "2009",
month = nov,
day = "1",
language = "English",
volume = "44",
pages = "2873--2880",
journal = "IEEE JOURNAL OF SOLID-STATE CIRCUITS",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
}