Parvais, B., Scheir, K., Vidojkovic, V., Vandebriel, R., Vandersteen, G., Soens, C., & Wambacq, P. (2010). A 40 nm LP CMOS PLL for high-speed mm-wave communication. In Proceedings of the ESSCIRC'10 conference, Seville, 13-17 Sept. 2010 (pp. 254)

@inproceedings{da5bdd04deed49f39be20bdf28c1c9dd,
title = "A 40 nm LP CMOS PLL for high-speed mm-wave communication",
abstract = "A phase-locked loop (PLL) that can be used in a zero-IF radio architecture with beamforming for AV-OFDM with 16-QAM modulation is demonstrated for the first time in 40 nm LP CMOS technology. This type II integer-N PLL of order four includes an injection-locked divide-by-4 prescaler and two quadrature series-coupled VCOs, operating in 63-70 GHz and 72-81 GHz frequency bands. It achieves -85 dBc/Hz in-band phase noise at 64 GHz, corresponding to -19.4 dBc integrated phase noise, while consuming 60 mA from a 1.1 V supply.",
keywords = "radio architecture, communication",
author = "Bertrand Parvais and Karen Scheir and Vojkan Vidojkovic and Roeland Vandebriel and Gerd Vandersteen and Charlotte Soens and Piet Wambacq",
year = "2010",
month = sep,
day = "13",
language = "English",
isbn = "978-1-4244-6662-7",
pages = "254",
booktitle = "Proceedings of the ESSCIRC'10 conference, Seville, 13-17 Sept. 2010",
note = "Unknown ; Conference date: 13-09-2010",
}