Acoustic cameras allow the visualization of sound sources using microphone arrays and beamforming techniques. The required computational power increases with the number of microphones in the array, the acoustic images resolution, and in particular, when targeting real-time. Such a constraint limits the use of acoustic cameras in many wireless sensor network applications (surveillance, industrial monitoring, etc.). In this paper, we propose a multi-mode System-on-Chip (SoC) Field-Programmable Gate Arrays (FPGA) architecture capable to satisfy the high computational demand while providing wireless communication for remote control and monitoring. This architecture produces real-time acoustic images of 240 × 180 resolution scalable to 640 × 480 by exploiting the multithreading capabilities of the hard-core processor. Furthermore, timing cost for different operational modes and for different resolutions are investigated to maintain a real time system under Wireless Sensor Networks constraints.
Vandendriessche, J , da Silva, B , Lhoest, LC , Braeken, A & Touhafi, A 2021, ' M3-AC: A Multi-Mode Multithread SoC FPGA Based Acoustic Camera ', Electronics , vol. 10, no. 3, 317, pp. 1-36.
Vandendriessche, J. , da Silva, B. , Lhoest, L. C. , Braeken, A. , & Touhafi, A. (2021). M3-AC: A Multi-Mode Multithread SoC FPGA Based Acoustic Camera . Electronics , 10 (3), 1-36. [317].
@article{d0023969b21149ba8ddb9f6327e026b6,
title = " M3-AC: A Multi-Mode Multithread SoC FPGA Based Acoustic Camera " ,
abstract = " Acoustic cameras allow the visualization of sound sources using microphone arrays and beamforming techniques. The required computational power increases with the number of microphones in the array, the acoustic images resolution, and in particular, when targeting real-time. Such a constraint limits the use of acoustic cameras in many wireless sensor network applications (surveillance, industrial monitoring, etc.). In this paper, we propose a multi-mode System-on-Chip (SoC) Field-Programmable Gate Arrays (FPGA) architecture capable to satisfy the high computational demand while providing wireless communication for remote control and monitoring. This architecture produces real-time acoustic images of 240 × 180 resolution scalable to 640 × 480 by exploiting the multithreading capabilities of the hard-core processor. Furthermore, timing cost for different operational modes and for different resolutions are investigated to maintain a real time system under Wireless Sensor Networks constraints. " ,
keywords = " Acoustic Camera, SoC FPGA, Hardware-Software co-design, Multi-mode, Multihread, Delay-and-Sum Beamforming, Wireless Sensor Networks " ,
author = " Jurgen Vandendriessche and {da Silva}, Bruno and Lhoest, {Lancelot Charles} and An Braeken and Abdellah Touhafi " ,
year = " 2021 " ,
month = feb,
day = " 1 " ,
doi = " 10.3390/electronics10030317 " ,
language = " English " ,
volume = " 10 " ,
pages = " 136 " ,
journal = " Electronics " ,
issn = " 2079-9292 " ,
publisher = " MDPI AG " ,
number = " 3 " ,
}