Wambacq, P., Verbruggen, B., Scheir, K., Borremans, J., De Heyn, V., Van Der Plas, G., Mercha, A., Parvais, B., Subramanian, V., Jurzak, M., Decoutere, S., & Donnay, S. (2006). Analog and RF circuits in 45 nm CMOS: planar bulk versus FinFET. In Proceedings of ESSCIRC-ESSDIRC (pp. 54-57). (Proceedings of ESSCIRC-ESSDIRC).

@inproceedings{88fcafa5d5344ee286d451a57d2fc390,
title = "Analog and RF circuits in 45 nm CMOS: planar bulk versus FinFET",
abstract = "Scaling to 45 nm node and below might necessitate the use of new processing steps (e.g. new gate stacks) or new device concepts such as FinFETs. Although intrinsic transistor speed increases with scaling, some analog performance parameters tend to degrade. In this paper we show with experimental results and simulations on analog and RF circuits that for high-speed and RF applications, downscaling to 45 nm channel length of bulk devices still improves RF circuit performance, while for low-frequency, high-gain applications FinFET technology offers better circuit performance than planar bulk CMOS.",
keywords = "CMOS, scaling",
author = "Piet Wambacq and Bob Verbruggen and Karen Scheir and Jonathan Borremans and {De Heyn}, V. and {Van Der Plas}, G. and A. Mercha and Bertrand Parvais and V. Subramanian and M. Jurzak and S. Decoutere and S. Donnay",
year = "2006",
month = sep,
day = "19",
language = "English",
series = "Proceedings of ESSCIRC-ESSDIRC",
pages = "54--57",
booktitle = "Proceedings of ESSCIRC-ESSDIRC",
note = "Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet ; Conference date: 21-09-2009 Through 25-09-2009",
}