This paper presents a 28 nm cryo-CMOS system-on-chip (SoC) for the dispersive readout of superconducting qubits operating between 6.5-8.1 GHz at 4 K. The SoC includes a quadrature VCO and a full zero-IF transmitter and receiver chain, including 200 MS/s7-bit DACs, ADCs, and digital. It can generate pulses up to 640 ns duration, and it attains a very low-power readout operation (9.8 mW) compared to its counterparts with 0.5-0.6 dB noise figure, 65-89 dB gain, and-71 dBm maximum TX output power at 4 K. Furthermore, with its duty-cycled mode, the SoC reduces the average power dissipation for the readout application.
Winckel, SV, Caglar, A, Gys, B, Brebels, S, Potocnik, A, Parvais, B, Wambacq, P & Craninckx, J 2022, A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-on-Chip for Superconducting Qubit Readout. in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC). ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings, IEEE, pp. 61-64, ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 19/09/22. https://doi.org/10.1109/esscirc55480.2022.9911493
Winckel, S. V., Caglar, A., Gys, B., Brebels, S., Potocnik, A., Parvais, B., Wambacq, P., & Craninckx, J. (2022). A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-on-Chip for Superconducting Qubit Readout. In ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) (pp. 61-64). (ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings). IEEE. https://doi.org/10.1109/esscirc55480.2022.9911493
@inproceedings{1c520ddc3ecf477ca27a07cdb5b089aa,
title = "A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-on-Chip for Superconducting Qubit Readout",
abstract = "This paper presents a 28 nm cryo-CMOS system-on-chip (SoC) for the dispersive readout of superconducting qubits operating between 6.5-8.1 GHz at 4 K. The SoC includes a quadrature VCO and a full zero-IF transmitter and receiver chain, including 200 MS/s7-bit DACs, ADCs, and digital. It can generate pulses up to 640 ns duration, and it attains a very low-power readout operation (9.8 mW) compared to its counterparts with 0.5-0.6 dB noise figure, 65-89 dB gain, and-71 dBm maximum TX output power at 4 K. Furthermore, with its duty-cycled mode, the SoC reduces the average power dissipation for the readout application. ",
author = "Winckel, {Steven Van} and Alican Caglar and Benjamin Gys and Steven Brebels and Anton Potocnik and Bertrand Parvais and Piet Wambacq and Jan Craninckx",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE. Copyright: Copyright 2022 Elsevier B.V., All rights reserved.; ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2022 ; Conference date: 19-09-2022 Through 22-09-2022",
year = "2022",
month = sep,
day = "19",
doi = "10.1109/esscirc55480.2022.9911493",
language = "English",
series = "ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings",
publisher = "IEEE",
pages = "61--64",
booktitle = "ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)",
}