Cost-effective implementations of wireless transceivers must have a small size and a low power consumption. To this purpose the degree of integration should be increased. This requires new front-end architectures and will result into ICs which combine analog and digital circuits. The development of front-end architectures is best supported by simulations at the architectural level. Current methodologies and corresponding tools suffer from common drawbacks, such as lack of accuracy, long simulation times, etc. A new methodology has been developed for efficient simulation, at the architectural level, of mixed-signal front-ends of digital telecom transceivers. The efficient execution is obtained using a local multirate, multicarrier signal respresentation together with a dataflow simulation scheme that dynamically switches to the most efficient signal processing technique available. The methodology has been implemented in the program FAST (Front-end Architecture Simulator for digital Telecom applications).
Vandersteen, G, Wambacq, P, Donnay, S, Rolain, Y & Eberle, W 2001, FAST: an efficient high-level dataflow simulator of mixed-signal front-ends of digital telecom transceivers. in P Wambacq, G Gielen & J Gerrits (eds), Chapter in: Low-power design techniques and CAD tools for analog and RF integrated circuits. Kluwer Academic Publishers, pp. 43-59.
Vandersteen, G., Wambacq, P., Donnay, S., Rolain, Y., & Eberle, W. (2001). FAST: an efficient high-level dataflow simulator of mixed-signal front-ends of digital telecom transceivers. In P. Wambacq, G. Gielen, & J. Gerrits (Eds.), Chapter in: Low-power design techniques and CAD tools for analog and RF integrated circuits (pp. 43-59). Kluwer Academic Publishers.
@inbook{4c9ebe91c3954d539a6794686d299620,
title = "FAST: an efficient high-level dataflow simulator of mixed-signal front-ends of digital telecom transceivers",
abstract = "Cost-effective implementations of wireless transceivers must have a small size and a low power consumption. To this purpose the degree of integration should be increased. This requires new front-end architectures and will result into ICs which combine analog and digital circuits. The development of front-end architectures is best supported by simulations at the architectural level. Current methodologies and corresponding tools suffer from common drawbacks, such as lack of accuracy, long simulation times, etc. A new methodology has been developed for efficient simulation, at the architectural level, of mixed-signal front-ends of digital telecom transceivers. The efficient execution is obtained using a local multirate, multicarrier signal respresentation together with a dataflow simulation scheme that dynamically switches to the most efficient signal processing technique available. The methodology has been implemented in the program FAST (Front-end Architecture Simulator for digital Telecom applications).",
keywords = "Front-end Archit. Simulator for digital Telecom",
author = "Gerd Vandersteen and Piet Wambacq and S. Donnay and Yves Rolain and Wolfgang Eberle",
note = "P. Wambacq, G. Gielen, J. Gerrits",
year = "2001",
month = jan,
day = "1",
language = "English",
isbn = "0-7923-7432-0",
pages = "43--59",
editor = "P. Wambacq and G. Gielen and J. Gerrits",
booktitle = "Chapter in: Low-power design techniques and CAD tools for analog and RF integrated circuits",
publisher = "Kluwer Academic Publishers",
address = "Netherlands",
}