Lynn Bos, Gerd Vandersteen, Pieter Rombouts, Arnd Geis, Alonso Morgado, Yves Rolain, G. Van Der Plas, Julien Ryckaert
This paper shows that multirate processing in a cascaded discrete-time 16 modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time 16 modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded 16 modulator enables the power efficient implementation of multiple communication standards. The advantages of multirate cascaded 16 modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time 16 modulator. A 2-1 multirate low-pass cascade, with a sa
Bos, L, Vandersteen, G, Rombouts, P, Geis, A, Morgado, A, Rolain, Y, Van Der Plas, G & Ryckaert, J 2010, 'Multirate Cascaded Discrete-Time Lowpass Delta Sigma Modulator for GSM/Bluetooth/UMTS', IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 45, no. 6, pp. 1198-1208.
Bos, L., Vandersteen, G., Rombouts, P., Geis, A., Morgado, A., Rolain, Y., Van Der Plas, G., & Ryckaert, J. (2010). Multirate Cascaded Discrete-Time Lowpass Delta Sigma Modulator for GSM/Bluetooth/UMTS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 45(6), 1198-1208.
@article{5328c7f073cc49b2baa2d480de897311,
title = "Multirate Cascaded Discrete-Time Lowpass Delta Sigma Modulator for GSM/Bluetooth/UMTS",
abstract = "This paper shows that multirate processing in a cascaded discrete-time 16 modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time 16 modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded 16 modulator enables the power efficient implementation of multiple communication standards. The advantages of multirate cascaded 16 modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time 16 modulator. A 2-1 multirate low-pass cascade, with a sa",
keywords = "Cascade, CMOS, delta sigma modulation, multi-mode, multirate, sigma delta modulation",
author = "Lynn Bos and Gerd Vandersteen and Pieter Rombouts and Arnd Geis and Alonso Morgado and Yves Rolain and {Van Der Plas}, G. and Julien Ryckaert",
year = "2010",
month = jun,
day = "1",
language = "English",
volume = "45",
pages = "1198--1208",
journal = "IEEE JOURNAL OF SOLID-STATE CIRCUITS",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "6",
}