Multimedia applications emerge on portable devices everywhere. These applications typically have a number of stringent requirements: (i) a high amount of computational power together with real-time performance and (ii) the flexibility to modify the application or the characteristics of the application at will. The performance requirements often drive the design towards a hardware implementation while the flexibility requirement is better served by a software implementation. In this paper we try to reconcile these two requirements by using an FPGA to implement the performance critical parts of a scalable wavelet video decoder. Through analytical means we first explore the performance and resource requirements. We find that modern FPGAs offer enough computational power to obtain real-time performance of the decoder, but that reaching the necessary memory bandwidth will be a challenge during this design.
Schelkens, P, Verdicchio, F, Devos, H, Eeckhaut, H & Stroobandt, D 2004, 'Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements', Computer Systems: Architectures, Modeling and Simulation, vol. 3133, pp. 203-212.
Schelkens, P., Verdicchio, F., Devos, H., Eeckhaut, H., & Stroobandt, D. (2004). Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements. Computer Systems: Architectures, Modeling and Simulation, 3133, 203-212.
@article{f35b8c1062964fb496265d90bf7fc6ec,
title = "Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements",
abstract = "Multimedia applications emerge on portable devices everywhere. These applications typically have a number of stringent requirements: (i) a high amount of computational power together with real-time performance and (ii) the flexibility to modify the application or the characteristics of the application at will. The performance requirements often drive the design towards a hardware implementation while the flexibility requirement is better served by a software implementation. In this paper we try to reconcile these two requirements by using an FPGA to implement the performance critical parts of a scalable wavelet video decoder. Through analytical means we first explore the performance and resource requirements. We find that modern FPGAs offer enough computational power to obtain real-time performance of the decoder, but that reaching the necessary memory bandwidth will be a challenge during this design.",
keywords = "scalable wavelet video, reconfigurable computing, FPGA",
author = "Peter Schelkens and Fabio Verdicchio and Harald Devos and Hendrik Eeckhaut and D. Stroobandt",
note = "Lecture Notes in Computer Science, Vol. 3133, pp. 203-212, .",
year = "2004",
language = "English",
volume = "3133",
pages = "203--212",
journal = "Computer Systems: Architectures, Modeling and Simulation",
}