CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeter-wave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz.
Wambacq, P, Verbruggen, B, Scheir, K, Borremans, J, Dehan, M, Linten, D, De Heyn, V, Van Der Plas, G, Mercha, A, Parvais, B, Gustin, C, Subramanian, V, Collaert, N, Jurczak, M & Decoutere, S 2007, 'The potential of FinFETs for analog and RF circuit applications', IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 11, pp. 2541-2551.
Wambacq, P., Verbruggen, B., Scheir, K., Borremans, J., Dehan, M., Linten, D., De Heyn, V., Van Der Plas, G., Mercha, A., Parvais, B., Gustin, C., Subramanian, V., Collaert, N., Jurczak, M., & Decoutere, S. (2007). The potential of FinFETs for analog and RF circuit applications. IEEE Transactions on Circuits and Systems I: Regular Papers, 54(11), 2541-2551.
@article{034d516d4a864c969561dc542b35fd56,
title = "The potential of FinFETs for analog and RF circuit applications",
abstract = "CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeter-wave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz.",
keywords = "FinFET, CMOS, RF, analog integrated circuits",
author = "Piet Wambacq and Bob Verbruggen and Karen Scheir and Jonathan Borremans and M. Dehan and Dimitri Linten and {De Heyn}, V. and {Van Der Plas}, G. and A. Mercha and Bertrand Parvais and Cedric Gustin and V. Subramanian and Nadine Collaert and M. Jurczak and S. Decoutere",
year = "2007",
language = "English",
volume = "54",
pages = "2541--2551",
journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "11",
}