Battery-powered edge systems must operate under tight energy budgets while facing growing computational demand from rapidly evolving edge workloads. Field-programmable gate arrays (FPGAs) offer middle ground when optimized for energy, especially flash-based FPGAs due to inherent low-power characteristics. Microchip flash-based SoC FPGAs further expose ultra-low-power (LP) modes including fabric Flash*Freeze (F*F), processor sleep and selectable standby clocks. Combining these modes with HW/SW partitioning and clock-frequency scaling can reduce energy for low-duty-cycle workloads; however, selecting an energy-efficient operating point in this multidimensional design space is non-trivial. This work explores the design space by measuring and analyzing LP modes across three architectural approaches (SW, co-design, and HW) under frequency scaling on a Microchip Smartfusion2 platform, using a low-duty-cycle heart-rate monitoring workload. Measurements indicate that, for low-duty-cycle workloads, total energy is dominated by the idle phase and is minimized by combining fabric-F*F with processor sleep. The results further show that main-clock downscaling reduces active-phase current but has limited impact on idle consumption once F*F and sleep are applied, while standby-clock selection trades idle current against LP entry/exit latency. Event-rate scaling further shows that the energy-optimal operating point can shift with duty cycle. We provide measurement-based guidelines for duty-cycle-aware energy-efficient operating point selection in similar flash-based SoC platforms.
Khan, MI, Becerra Machado, NR, Nassihi, A, Sadaqa, A & da Silva, B 2026, 'Exploiting Low-Power Techniques of a Flash-Based SoC FPGA for Energy-Efficient Edge Processing', Applied Sciences, vol. 16, no. 6, 2648, pp. 1-29. https://doi.org/10.3390/app16062648
Khan, M. I., Becerra Machado, N. R., Nassihi, A., Sadaqa, A., & da Silva, B. (2026). Exploiting Low-Power Techniques of a Flash-Based SoC FPGA for Energy-Efficient Edge Processing. Applied Sciences, 16(6), 1-29. Article 2648. https://doi.org/10.3390/app16062648
@article{1b477a32a06c49498efa855cd11ed178,
title = "Exploiting Low-Power Techniques of a Flash-Based SoC FPGA for Energy-Efficient Edge Processing",
abstract = "Battery-powered edge systems must operate under tight energy budgets while facing growing computational demand from rapidly evolving edge workloads. Field-programmable gate arrays (FPGAs) offer middle ground when optimized for energy, especially flash-based FPGAs due to inherent low-power characteristics. Microchip flash-based SoC FPGAs further expose ultra-low-power (LP) modes including fabric Flash*Freeze (F*F), processor sleep and selectable standby clocks. Combining these modes with HW/SW partitioning and clock-frequency scaling can reduce energy for low-duty-cycle workloads; however, selecting an energy-efficient operating point in this multidimensional design space is non-trivial. This work explores the design space by measuring and analyzing LP modes across three architectural approaches (SW, co-design, and HW) under frequency scaling on a Microchip Smartfusion2 platform, using a low-duty-cycle heart-rate monitoring workload. Measurements indicate that, for low-duty-cycle workloads, total energy is dominated by the idle phase and is minimized by combining fabric-F*F with processor sleep. The results further show that main-clock downscaling reduces active-phase current but has limited impact on idle consumption once F*F and sleep are applied, while standby-clock selection trades idle current against LP entry/exit latency. Event-rate scaling further shows that the energy-optimal operating point can shift with duty cycle. We provide measurement-based guidelines for duty-cycle-aware energy-efficient operating point selection in similar flash-based SoC platforms.",
keywords = "low power, energy efficiency, power/energy optimization, low-power modes, clock-frequency scaling, flash-based SoC FPGA, Flash*Freeze, energy-latency trade-off, duty-cycled sensing, HW/SW partitioning, Edge computing",
author = "Khan, \{Muhammad Iqbal\} and \{Becerra Machado\}, \{Nicolas Roberto\} and Abdessamad Nassihi and Ahmed Sadaqa and \{da Silva\}, Bruno",
note = "Publisher Copyright: {\textcopyright} 2026 by the authors.",
year = "2026",
month = mar,
day = "10",
doi = "10.3390/app16062648",
language = "English",
volume = "16",
pages = "1--29",
journal = "Applied Sciences",
issn = "2076-3417",
publisher = "MDPI",
number = "6",
}