Das, S., Riedel, S., Bertuletti, M., Benini, L., Brunion, M., Ryckaert, J., Myers, J., Biswas, D., & Milojevic, D. (2024). 3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs. In 2024 IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE International Symposium on Circuits and Systems proceedings). IEEE. https://doi.org/10.1109/ISCAS58744.2024.10558687

@inproceedings{8ac7f1c8ff3c457bbe988db64d0e8608,
title = "3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs",
abstract = "This paper presents an investigation of System-on-Chip (SoC) communication latency optimization for 3D system integration and highlights the role of architectural modifications to maximize the Power, Performance, \& Area (PPA) benefits. An instance of a highly configurable RISC-V SoC is implemented using ∼2nm nanosheet technology and different 3D stacking options using design flow from sign-off tools. The proposed implementation targets performance optimization for different 3D partitioning scenarios: Memory-on-Logic (MoL) \& Logic-on-Logic (LoL). We target 2-die 3D Integrated Circuits (3D-IC) with high density 3D interconnect using Face-to-Face (F2F) hybrid bonding (∼1µm), and 3-die stack, as Face-to-Back (F2B) on top of F2F. Our analysis of the 16-core SoC instance shows that the proposed architectural optimizations bring a significant reduction of 4 pipeline stages in the design hierarchy at a marginal cost of 9\% effective frequency loss when implemented in 3D in comparison to the baseline 2D architecture. Further, going from 2D to 3D allows more than 40\% total system wire-length reduction \& 10\% less cell area, resulting in 20\% power savings. These findings hold promise for further explorations on many-core SoC instances (256 \& more) facing system interconnect challenges.",
author = "Sudipta Das and Samuel Riedel and Marco Bertuletti and Luca Benini and Moritz Brunion and Julien Ryckaert and James Myers and Dwaipayan Biswas and Dragomir Milojevic",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 IEEE International Symposium on Circuits and Systems (ISCAS) ; Conference date: 19-05-2024 Through 22-05-2024",
year = "2024",
doi = "10.1109/ISCAS58744.2024.10558687",
language = "English",
series = "IEEE International Symposium on Circuits and Systems proceedings",
publisher = "IEEE",
booktitle = "2024 IEEE International Symposium on Circuits and Systems (ISCAS)",
url = "https://2024.ieee-iscas.org/",
}