Publication Details
Overview
 
 
A. Vandooren, Z. Wu, N. Parihar, J. Franco, Bertrand Parvais, P. Matagne, H. Debruyn, G. Mannaert, K. Devriendt, L. Teugels, E. Vecchio, D. Radisic, E. Rosseel, A. Hikavyy, B. T. Chan, N. Waldron, J. Mitard, G. Besnard, A. Alvarez, G. Gaudin, ne_list"W. Schwarzenbach, I. Radu, B. Y. Nguyen, K. Huet, T. Tabata, F. Mazzamuto, S. Demuynck, J. Boemmels, N. Collaert, N. Horiguchi, N. Horiguchi/span
 

2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings

Contribution To Book Anthology

Abstract 

Top tier devices in a 3D sequential integration are optimized using a low temperature process flow (< 525°C}). Bi-axial tensile strained silicon is transferred without strain relaxation to boost the top tier nmos device performance by 40-50% over the unstrained silicon devices, recovering the performance loss from the low temperature processing when using extension-less device integration. Excimer laser anneal is also shown to effectively activate both n-type and p-type dopants in the extension of thin silicon film devices using optimized, CMOS compatible, laser exposure conditions. Laser anneal is fully compatible with a replacement metal gate (RMG) process flow and with selective source/drain (SD) epitaxy. The dopant activation level is preserved during the entire process flow which results in similar Ion Ioff device performance for devices with laser and spike anneals. Excimer laser anneal benefits also from improved control short channel effects over spike annealing due to low dopant diffusion.

Reference 
 
 
DOI scopus