This work presents a discrete-time (DT) delta sigma modulator (DSM) ADC that uses ring amplifiers to relax critical speed and efficiency bottlenecks. The DSM is designed as a 3 rd -order Cascade of Integrator with Feed Forward (CIFF) with a 4-bit quantizer, and it achieves a peak SNDR of 67dB and DR of 70.0dB with 47.5MHz bandwidth when clocked at 950MHz. This is the highest bandwidth reported to-date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7mW from a 1V supply, FOMs and FOMw are 167.0dB and 27.0fJ/c.s. respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth.
Moura Santana, L, Martens, E, Lagos Benites, JL, Hershberg, B, Wambacq, P & Craninckx, J 2021, A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC). ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings, IEEE, Grenoble, France, pp. 207-210, IEEE 47th European Solid State Circuits Conference, Grenoble, France, 13/09/21. https://doi.org/10.1109/ESSCIRC53450.2021.9567814
Moura Santana, L., Martens, E., Lagos Benites, J. L., Hershberg, B., Wambacq, P., & Craninckx, J. (2021). A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) (pp. 207-210). (ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings). IEEE. https://doi.org/10.1109/ESSCIRC53450.2021.9567814
@inproceedings{09c7307f2018450d97c0720b19a46e8f,
title = "A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC",
abstract = "This work presents a discrete-time (DT) delta sigma modulator (DSM) ADC that uses ring amplifiers to relax critical speed and efficiency bottlenecks. The DSM is designed as a 3 rd -order Cascade of Integrator with Feed Forward (CIFF) with a 4-bit quantizer, and it achieves a peak SNDR of 67dB and DR of 70.0dB with 47.5MHz bandwidth when clocked at 950MHz. This is the highest bandwidth reported to-date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7mW from a 1V supply, FOMs and FOMw are 167.0dB and 27.0fJ/c.s. respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth.",
keywords = "ADC, CMOS, delta sigma modulation",
author = "{Moura Santana}, Lucas and Ewout Martens and {Lagos Benites}, {Jorge Luis} and Benjamin Hershberg and Piet Wambacq and Jan Craninckx",
year = "2021",
month = sep,
day = "13",
doi = "10.1109/ESSCIRC53450.2021.9567814",
language = "English",
series = "ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings",
publisher = "IEEE",
pages = "207--210",
booktitle = "ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)",
note = "IEEE 47th European Solid State Circuits Conference, ESSCIRC ; Conference date: 13-09-2021 Through 17-09-2021",
url = "https://www.esscirc-essderc2021.org/",
}