We present a two-way current combining power amplifier (PA) for 28GHz wireless communication. To boost the saturated output power (P SAT ) and maintain a high power-added efficiency (PAE), a differential 3-stacked transistors structure is used for the unit PA cell. The stability factor and the PAE are improved with capacitive neutralization and shunt inductor intermediate node matching. Reliability issues under a 2.4V supply voltage are relieved with properly designed biasing and gate capacitances. The PA is implemented in a 22nm FD-SOI technology with a chip core area of 0.21 mm 2 , Measurement results show that the PA achieves a power gain of 27dB and a PSAT of 21.7dBm with a maximum PAE of 27.1% at 28GHz. The output 1dB compression point (P 1aB ) is 19.1 dBm. Measured PAE at P 1dB and 6dB power back-off are 23% and 10.3%, respectively.
Zong, Z , Tang, X , Nguyen, JH-D , Khalaf, K, Mangraviti, G, Liu, Y & Wambacq, P 2020, A 28GHz Two-Way Current Combining Stacked-FET Power Amplifier in 22nm FD-SOI . in 2020 IEEE Custom Integrated Circuits Conference (CICC). pp. 1-4, 2020 IEEE Custom Integrated Circuits Conference (CICC), United States, 22/03/19 .
Zong, Z. , Tang, X. , Nguyen, J. H-D. , Khalaf, K., Mangraviti, G., Liu, Y. , & Wambacq, P. (2020). A 28GHz Two-Way Current Combining Stacked-FET Power Amplifier in 22nm FD-SOI . In 2020 IEEE Custom Integrated Circuits Conference (CICC) (pp. 1-4)
@inproceedings{ebda31fffd584af19168bf028ec2ba9f,
title = " A 28GHz Two-Way Current Combining Stacked-FET Power Amplifier in 22nm FD-SOI " ,
abstract = " We present a two-way current combining power amplifier (PA) for 28GHz wireless communication. To boost the saturated output power (PSAT) and maintain a high power-added efficiency (PAE), a differential 3-stacked transistors structure is used for the unit PA cell. The stability factor and the PAE are improved with capacitive neutralization and shunt inductor intermediate node matching. Reliability issues under a 2.4V supply voltage are relieved with properly designed biasing and gate capacitances. The PA is implemented in a 22nm FD-SOI technology with a chip core area of 0.21 mm2, Measurement results show that the PA achieves a power gain of 27dB and a PSAT of 21.7dBm with a maximum PAE of 27.1% at 28GHz. The output 1dB compression point (P1aB) is 19.1 dBm. Measured PAE at P1dB and 6dB power back-off are 23% and 10.3%, respectively. " ,
author = " Zhiwei Zong and Xinyan Tang and Nguyen, {Johan Hoang-Dung} and Khaled Khalaf and Giovanni Mangraviti and Yao Liu and Piet Wambacq " ,
year = " 2020 " ,
month = mar,
doi = " 10.1109/cicc48029.2020.9075906 " ,
language = " English " ,
isbn = " 9781728160313 " ,
pages = " 14 " ,
booktitle = " 2020 IEEE Custom Integrated Circuits Conference (CICC) " ,
note = " 2020 IEEE Custom Integrated Circuits Conference (CICC) Conference date: 22-03-2019 Through 25-03-2020 " ,
}