This paper presents a 12 bit, 4.7 MS/s Digital Feed-Forward Incremental ΣΔ - Successive Approximation Register (DFF I- ΣΔ -SAR) Analog-to-Digital Converter (ADC) for column readout of image sensors. An input range detection phase and a new switching scheme for the DAC in the first stage allow reaching the desired 4 bit resolution of the I- ΣΔ stage with an Over Sampling Ratio (OSR) of 8. A second stage SAR converts the I- ΣΔ residue voltage resolving the 8 Least Significant Bits (LSBs). The ADC is integrated in a test chip with a Source Follower (SF) test unit that emulates a pixel array and is fabricated using 2-Poly-4-Metal 130 nm CMOS technology. The ADC operates under 3.3 V/1.2 V supply voltages, achieving a DNL of −0.43/0.62 12 bit LSBs, 356 μV rms noise, equivalent to 9.2 bit ENOB at a sampling frequency of 4.7 MS/s with an OSR of 8. The proposed ADC consumes 260.5 μW of power, yielding a Walden Figure-of-Merit 94 fJ/c.s.. The core area is 18400 μm2 .
Frazzica, F, Yasue, T, Spagnolo, A, Bello, DSS, De Bock, M, Craninckx, J & Wambacq, P 2021, 'A 12 Bit 4.7-MS/s 260.5μW Digital Feed-Forward Incremental-ΣΔ-SAR ADC in 0.13μm CMOS for Image Sensors', IEEE Sensors Journal, vol. 21, no. 19, pp. 21653-21666. https://doi.org/10.1109/JSEN.2021.3102082
Frazzica, F., Yasue, T., Spagnolo, A., Bello, D. S. S., De Bock, M., Craninckx, J., & Wambacq, P. (2021). A 12 Bit 4.7-MS/s 260.5μW Digital Feed-Forward Incremental-ΣΔ-SAR ADC in 0.13μm CMOS for Image Sensors. IEEE Sensors Journal, 21(19), 21653-21666. https://doi.org/10.1109/JSEN.2021.3102082
@article{92f518b744244c68a83b16c91b3d3720,
title = "A 12 Bit 4.7-MS/s 260.5μW Digital Feed-Forward Incremental-ΣΔ-SAR ADC in 0.13μm CMOS for Image Sensors",
abstract = "This paper presents a 12 bit, 4.7 MS/s Digital Feed-Forward Incremental ΣΔ - Successive Approximation Register (DFF I- ΣΔ -SAR) Analog-to-Digital Converter (ADC) for column readout of image sensors. An input range detection phase and a new switching scheme for the DAC in the first stage allow reaching the desired 4 bit resolution of the I- ΣΔ stage with an Over Sampling Ratio (OSR) of 8. A second stage SAR converts the I- ΣΔ residue voltage resolving the 8 Least Significant Bits (LSBs). The ADC is integrated in a test chip with a Source Follower (SF) test unit that emulates a pixel array and is fabricated using 2-Poly-4-Metal 130 nm CMOS technology. The ADC operates under 3.3 V/1.2 V supply voltages, achieving a DNL of −0.43/0.62 12 bit LSBs, 356 μV rms noise, equivalent to 9.2 bit ENOB at a sampling frequency of 4.7 MS/s with an OSR of 8. The proposed ADC consumes 260.5 μW of power, yielding a Walden Figure-of-Merit 94 fJ/c.s.. The core area is 18400 μm2 .",
keywords = "Analog to digital converter (ADC), CMOS image sensor (CIS), CMOS image sensor readout, incremental Sigma Delta ADC, successive approximation register (SAR) ADC, ultra-high-definition-tele-vision (UHTV), virtual-reality (VR), 16k resolution",
author = "Fortunato Frazzica and Toshio Yasue and Annachiara Spagnolo and Bello, \{David San Segundo\} and \{De Bock\}, Maarten and Jan Craninckx and Piet Wambacq",
note = "Publisher Copyright: {\textcopyright} 2001-2012 IEEE. Copyright: Copyright 2021 Elsevier B.V., All rights reserved.",
year = "2021",
month = oct,
day = "1",
doi = "10.1109/JSEN.2021.3102082",
language = "English",
volume = "21",
pages = "21653--21666",
journal = "IEEE Sensors Journal",
issn = "1530-437X",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "19",
}