Verbruggen, B., Craninckx, J., Kuijk, M., Wambacq, P., & Van Der Plas, G. (2010). A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 45, 2080-2090.

@article{a5347a2a76c648f782a0e57e5a5a22eb,
title = "A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS",
abstract = "A 2.2 GS/s 4 x -interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. The folding stage samples the input, removes its common-mode component and rectifies the differential voltage. The pipelined binary-search sub-ADC leverages threshold calibration to correct for amplifier and comparator imperfections, which allows the use of inherently nonlinear dynamic amplifiers. The prototype achieves 31.6 dB SNDR at 2.2 GS/s with a 2 GHz ERBW for 2.6 mW power consumption in an area of 0.03 mm(2)",
keywords = "Analog-digital conversion; calibration; CMOS analo",
author = "Bob Verbruggen and J. Craninckx and Maarten Kuijk and Piet Wambacq and \{Van Der Plas\}, G.",
year = "2010",
language = "English",
volume = "45",
pages = "2080--2090",
journal = "IEEE JOURNAL OF SOLID-STATE CIRCUITS",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
}