An 8-phase phase-aligned ring oscillator in 90 nm digital CMOS is presented that operates up to 2 GHz. The low-complexity circuit consumes 13 mW at 2 GHz and 1.2 mW at 400 MHz, while a flat in-band phase noise below -120 dBc/Hz is achieved, in close agreement with the presented theory. The circuit occupies an area of 0.008 mm(2).
Borremans, J, Ryckaert, J, Desset, C, Kuijk, M, Wambacq, P & Craninckx, J 2009, 'Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS', IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 44, no. 7, pp. 1942-1949.
Borremans, J., Ryckaert, J., Desset, C., Kuijk, M., Wambacq, P., & Craninckx, J. (2009). Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 44(7), 1942-1949.
@article{72a173182a15455a996568866e8d30eb,
title = "Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS",
abstract = "An 8-phase phase-aligned ring oscillator in 90 nm digital CMOS is presented that operates up to 2 GHz. The low-complexity circuit consumes 13 mW at 2 GHz and 1.2 mW at 400 MHz, while a flat in-band phase noise below -120 dBc/Hz is achieved, in close agreement with the presented theory. The circuit occupies an area of 0.008 mm(2).",
keywords = "Clock multiplier, low-voltage, realignment, ring oscillator",
author = "Jonathan Borremans and Julien Ryckaert and Claude Desset and Maarten Kuijk and Piet Wambacq and J. Craninckx",
year = "2009",
month = jul,
day = "1",
language = "English",
volume = "44",
pages = "1942--1949",
journal = "IEEE JOURNAL OF SOLID-STATE CIRCUITS",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "7",
}