The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced mismatch. Using an optimized integration to minimize parasitics we demonstrate high-performing FinFET ring-oscillators with delays down to 10ps/stage for both SOI and bulk FinFETs and working SRAM cells at VDD=1.0V.
Chiarella, T, Witters, L, Mercha, A, Kerner, C, Dittrich, R, Rakowski, M, Ortolland, C, Ragnarsson, LÃ…, Parvais, B, De Keersgieter, A, Kubicek, S, Redolfi, A, Rooyackers, R, Vrancken, C, Brus, S, Lauwers, A, Absil, P, Biesemans, S & Hoffmann, T 2009, Migrating from PLANAR to FinFET for further CMOS scaling: SOI or bulk? in ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference., 5325993, ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference, pp. 84-87, 35th European Solid-State Circuits Conference, ESSCIRC 2009, Athens, Greece, 14/09/09. https://doi.org/10.1109/ESSCIRC.2009.5325993
Chiarella, T., Witters, L., Mercha, A., Kerner, C., Dittrich, R., Rakowski, M., Ortolland, C., Ragnarsson, L. Ã…., Parvais, B., De Keersgieter, A., Kubicek, S., Redolfi, A., Rooyackers, R., Vrancken, C., Brus, S., Lauwers, A., Absil, P., Biesemans, S., & Hoffmann, T. (2009). Migrating from PLANAR to FinFET for further CMOS scaling: SOI or bulk? In ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference (pp. 84-87). Article 5325993 (ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2009.5325993
@inproceedings{57f1a97bf3c345308faa37cbc3a07bad,
title = "Migrating from PLANAR to FinFET for further CMOS scaling: SOI or bulk?",
abstract = "The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced mismatch. Using an optimized integration to minimize parasitics we demonstrate high-performing FinFET ring-oscillators with delays down to 10ps/stage for both SOI and bulk FinFETs and working SRAM cells at VDD=1.0V.",
author = "T. Chiarella and L. Witters and A. Mercha and C. Kerner and R. Dittrich and M. Rakowski and C. Ortolland and Ragnarsson, {L. {\AA}} and B. Parvais and {De Keersgieter}, A. and S. Kubicek and A. Redolfi and R. Rooyackers and C. Vrancken and S. Brus and A. Lauwers and P. Absil and S. Biesemans and T. Hoffmann",
year = "2009",
month = dec,
day = "1",
doi = "10.1109/ESSCIRC.2009.5325993",
language = "English",
isbn = "9781424443536",
series = "ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference",
pages = "84--87",
booktitle = "ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference",
note = "35th European Solid-State Circuits Conference, ESSCIRC 2009 ; Conference date: 14-09-2009 Through 18-09-2009",
}