We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13μm CMOS process on 200mm wafers. The top die is thinned down to 25μm and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process.
Van Olmen, J, Mercha, A, Katti, G, Huyghebaert, C, Van Aelst, J, Seppala, E, Chao, Z, Armini, S, Vaes, J, Teixeira, RC, Van Cauwenberghe, M, Verdonck K Verhemeldonck, P, Jourdain, A, Ruythooren, W, De Potter De Ten Broeck, M, Opdebeeck, A, Chiarella, T, Parvais, B, Debusschere, I, Hoffmann, TY, De Wachter, B, Dehaene, W, Stucchi, M, Rakowski, M, Soussan, P, Cartuyvels, R, Beyne, E, Biesemans, S & Swinnen, B 2008, 3D stacked IC demonstration using a through silicon via first approach. in 2008 IEEE International Electron Devices Meeting, IEDM 2008., 4796763, Technical Digest - International Electron Devices Meeting, IEDM, 2008 IEEE International Electron Devices Meeting, IEDM 2008, San Francisco, CA, United States, 15/12/08. https://doi.org/10.1109/IEDM.2008.4796763
Van Olmen, J., Mercha, A., Katti, G., Huyghebaert, C., Van Aelst, J., Seppala, E., Chao, Z., Armini, S., Vaes, J., Teixeira, R. C., Van Cauwenberghe, M., Verdonck K Verhemeldonck, P., Jourdain, A., Ruythooren, W., De Potter De Ten Broeck, M., Opdebeeck, A., Chiarella, T., Parvais, B., Debusschere, I., ... Swinnen, B. (2008). 3D stacked IC demonstration using a through silicon via first approach. In 2008 IEEE International Electron Devices Meeting, IEDM 2008 Article 4796763 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2008.4796763
@inproceedings{2adeed0b9b604d108353b2886f0c47f0,
title = "3D stacked IC demonstration using a through silicon via first approach",
abstract = "We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13μm CMOS process on 200mm wafers. The top die is thinned down to 25μm and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process.",
author = "{Van Olmen}, J. and A. Mercha and G. Katti and C. Huyghebaert and {Van Aelst}, J. and E. Seppala and Zhao Chao and S. Armini and J. Vaes and Teixeira, {R. Cotrin} and {Van Cauwenberghe}, M. and {Verdonck K Verhemeldonck}, P. and A. Jourdain and W. Ruythooren and {De Potter De Ten Broeck}, M. and A. Opdebeeck and T. Chiarella and B. Parvais and I. Debusschere and Hoffmann, {T. Y.} and {De Wachter}, B. and W. Dehaene and M. Stucchi and M. Rakowski and Ph Soussan and R. Cartuyvels and E. Beyne and S. Biesemans and B. Swinnen",
year = "2008",
month = dec,
day = "1",
doi = "10.1109/IEDM.2008.4796763",
language = "English",
isbn = "9781424423781",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
booktitle = "2008 IEEE International Electron Devices Meeting, IEDM 2008",
note = "2008 IEEE International Electron Devices Meeting, IEDM 2008 ; Conference date: 15-12-2008 Through 17-12-2008",
}