An 8-phase phase-aligned ring oscillator in 90 nm digital CMOS is presented that operates up to 2 GHz. The low-complexity circuit consumes 13 mW at 2 GHz and 1.2 mW at 400 MHz, while a flat in-band phase noise below -120 dBc/Hz is achieved, in close agreement with the presented theory. The circuit occupies an area of 0.008 mm(2).
Borremans, J, Ryckaert, J, Desset, C, Kuijk, M, Wambacq, P & Craninckx, J 2008, Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS. in Proceedings of ESSCIRC 2008 . IEEE, pp. 410-413, European Solid-State Circuits Conference (ESSCIRC), 15/09/08.
Borremans, J., Ryckaert, J., Desset, C., Kuijk, M., Wambacq, P., & Craninckx, J. (2008). Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS. In Proceedings of ESSCIRC 2008 (pp. 410-413). IEEE.
@inproceedings{0bc11512ab41417487268fe0adc9f4d9,
title = "Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS",
abstract = "An 8-phase phase-aligned ring oscillator in 90 nm digital CMOS is presented that operates up to 2 GHz. The low-complexity circuit consumes 13 mW at 2 GHz and 1.2 mW at 400 MHz, while a flat in-band phase noise below -120 dBc/Hz is achieved, in close agreement with the presented theory. The circuit occupies an area of 0.008 mm(2).",
keywords = "ring oscillator, realignment, Clock multiplier",
author = "Jonathan Borremans and Julien Ryckaert and Claude Desset and Maarten Kuijk and Piet Wambacq and J. Craninckx",
year = "2008",
month = sep,
day = "15",
language = "English",
isbn = "978-1-4244-2361-3",
pages = "410--413",
booktitle = "Proceedings of ESSCIRC 2008",
publisher = "IEEE",
note = "European Solid-State Circuits Conference (ESSCIRC) ; Conference date: 15-09-2008 Through 19-09-2008",
url = "http://www.esscirc.org, http://www.esscirc2008.org/",
}