Wambacq, P., Verbruggen, B., Scheir, K., Borremans, J., De Heyn, V., Van Der Plas, G., Mercha, A., Parvais, B., Subramanian, V., Jurczak, M., Decoutere, S., & Donnay, S. (2006). Analog and RF circuits in 45 nm CMOS and below: Planar bulk versus FinFET. In ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference (pp. 54-57). Article 4099702 (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIR.2006.307529

@inproceedings{4bf54e5e4e144ef1ab1dcbc8c4b643b7,
title = "Analog and RF circuits in 45 nm CMOS and below: Planar bulk versus FinFET",
abstract = "Scaling to 45 nm node and below might necessitate the use of new processing steps (e.g. new gate stacks) or new device concepts such as FinFETs. Although intrinsic transistor speed increases with scaling, some analog performance parameters tend to degrade. In this paper we show with experimental results and simulations on analog and RF circuits that for high-speed and RF applications, downscaling to 45 nm channel length of bulk devices still improves RF circuit performance, while for low-frequency, high-gain applications FinFET technology offers better circuit performance than planar bulk CMOS.",
author = "Piet Wambacq and Bob Verbruggen and Karen Scheir and Jonathan Borremans and {De Heyn}, Vincent and {Van Der Plas}, Geert and Abdelkarim Mercha and Bertrand Parvais and Vaidy Subramanian and Malgorzata Jurczak and Stefaan Decoutere and St{\'e}phane Donnay",
year = "2006",
month = dec,
day = "1",
doi = "10.1109/ESSCIR.2006.307529",
language = "English",
isbn = "1424403022",
series = "ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference",
pages = "54--57",
booktitle = "ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference",
note = "ESSCIRC 2006 - 32nd European Solid-State Circuits Conference ; Conference date: 19-09-2006 Through 21-09-2006",
}