The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to 5e-10Ωcm2 or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.
Schuddinck, P, Zografos, O, Weckx, P, Matagne, P, Sarkar, S, Sherazi, Y, Baert, R, Jang, D, Yakimets, D, Gupta, A, Parvais, B, Ryckaert, J, Verkest, D & Mocuta, A 2019, Device-, Circuit-Block-level evaluation of CFET in a 4 track library. in 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers., 8776513, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. T204-T205, 39th Symposium on VLSI Technology, VLSI Technology 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIT.2019.8776513
Schuddinck, P., Zografos, O., Weckx, P., Matagne, P., Sarkar, S., Sherazi, Y., Baert, R., Jang, D., Yakimets, D., Gupta, A., Parvais, B., Ryckaert, J., Verkest, D., & Mocuta, A. (2019). Device-, Circuit-Block-level evaluation of CFET in a 4 track library. In 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers (pp. T204-T205). Article 8776513 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2019.8776513
@inproceedings{29257afba23349f7be2b431360b91fa2,
title = "Device-, Circuit-Block-level evaluation of CFET in a 4 track library",
abstract = "The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to 5e-10Ωcm2 or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.",
author = "P. Schuddinck and O. Zografos and P. Weckx and P. Matagne and S. Sarkar and Y. Sherazi and R. Baert and D. Jang and D. Yakimets and A. Gupta and B. Parvais and J. Ryckaert and D. Verkest and A. Mocuta",
year = "2019",
month = jun,
day = "1",
doi = "10.23919/VLSIT.2019.8776513",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "T204--T205",
booktitle = "2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers",
address = "United States",
note = "39th Symposium on VLSI Technology, VLSI Technology 2019 ; Conference date: 09-06-2019 Through 14-06-2019",
}