Balachandran, J., Kuijk, M., Carchon, G., Nauwelaers, B., & Beyne, E. (2006). Efficient link architecture for on-chip serial links and networks. In International Symposium System-on-Chip Tampere, Finland (pp. 1-4). IEEE.

@inproceedings{ace334c171784f75b4b3efc29c4c7650,
title = "Efficient link architecture for on-chip serial links and networks",
abstract = "Serial links are an effective solution to address the growing on-chip communication bottlenecks in nano-CMOS technologies. This paper proposes efficient link architecture for on-chip serial links and networks. The proposed solution consists of a pre-emphasized differential driver and receiver interconnected by LC transmission lines. The LC transmission lines are implemented in packaging layers post processed directly above a standard CMOS wafer. The link enables simple register-to-register style data transfer, well suited for on-chip IO. The proposed scheme can offer data rates as high as 12.5 Gbps per channel for less than 0.5pJ of energy per bit on the 0.13 micron technology",
keywords = "on-chip links and networks",
author = "Jayaprakash Balachandran and Maarten Kuijk and G. Carchon and B. Nauwelaers and Eric Beyne",
year = "2006",
month = nov,
day = "14",
language = "English",
isbn = "978-1-4244-0621-0",
pages = "1--4",
booktitle = "International Symposium System-on-Chip Tampere, Finland",
publisher = "IEEE",
note = "Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet ; Conference date: 21-09-2009 Through 25-09-2009",
}