Publication Details
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Rana Yasser ElKashlan, R. Y. Elkashlan, R. Rodriguez, S. Yadav, A. Khaled, U. Peralagu, A. Alian, N. Waldron, M. Zhao, Piet Wambacq, Bertrand Parvais, N. Collaert
 

IEEE Transactions on Electron Devices

Contribution To Journal

Abstract 

To enable CMOS-compatible GaN HEMTs for the next generation of communication systems (5G and beyond), a low gate resistance is of great importance since it directly affects the RF power gain and fMAX of the transistor. In this article, the impact of various gate-metal stacks on the gate resistance and RF performance of the devices is studied. The optimized Ti-free gate-metal process leads to fMAX enhancement up to ~50% for devices scaled down to 0.32-µm gate lengths. The gate resistance for the T-shaped gate is modeled from the S-parameters and validated on various gate field plate geometries. The tradeoff between the gate resistance and the parasitic capacitance in GaN HEMTs is highlighted in this case.

Reference 
 
 
DOI scopus