In a first aspect, the present invention relates to an integrated circuit, comprising: i. a host substrate (100); ii. optionally, a first layer (200) overlaying the host substrate (100), the first layer (200) optionally comprising a first transistor (210); iii. a second layer (500) overlaying the host substrate (100) and the first layer (200), if present, the second layer (500) comprising a second transistor (510); and iv. an electromagnetic shielding structure (600) shielding the second transistor (510) from electromagnetic fields, comprising - a bottom (610, 611) underlaying the second transistor (510) and comprised in the host substrate (100), the first layer (200), if present, or the second layer (500), - one or more lateral sides (620, 621, 622) laterally bordering the second transistor (510), and - optionally, a top (630) overlaying the second transistor (510); wherein the bottom (610, 611), each of the one or more lateral sides (620, 621, 622) and, if present, the top (630) each comprise at least one shielding element independently made up of either an electrically conductive material or a trap-rich material.
Collaert, N, Parvais, B & van Liempd, B, Shielding in an integrated circuit, Patent No. EP3460842A.
Collaert, N., Parvais, B., & van Liempd, B. (2019). Shielding in an integrated circuit. (Patent No. EP3460842A).
@misc{c07b8ba6794241e188391dd61fc96a1d,
title = "Shielding in an integrated circuit",
abstract = "In a first aspect, the present invention relates to an integrated circuit, comprising: i. a host substrate (100); ii. optionally, a first layer (200) overlaying the host substrate (100), the first layer (200) optionally comprising a first transistor (210); iii. a second layer (500) overlaying the host substrate (100) and the first layer (200), if present, the second layer (500) comprising a second transistor (510); and iv. an electromagnetic shielding structure (600) shielding the second transistor (510) from electromagnetic fields, comprising - a bottom (610, 611) underlaying the second transistor (510) and comprised in the host substrate (100), the first layer (200), if present, or the second layer (500), - one or more lateral sides (620, 621, 622) laterally bordering the second transistor (510), and - optionally, a top (630) overlaying the second transistor (510); wherein the bottom (610, 611), each of the one or more lateral sides (620, 621, 622) and, if present, the top (630) each comprise at least one shielding element independently made up of either an electrically conductive material or a trap-rich material.",
author = "Nadine Collaert and Bertrand Parvais and {van Liempd}, Barend",
year = "2019",
language = "English",
type = "Patent",
note = "EP3460842A",
}