This paper presents design considerations and methodology for D-band transformer-based Class-AB gain-boosting power amplifiers (PAs) in three advanced silicon technologies: 28 nm bulk CMOS (complementary metal oxide semiconductor), 22 nm FD-SOI (fully-depleted silicon on insulator), and 130 nm SiGe BiCMOS (Silicon-germanium bipolar-CMOS). Firstly, the choice of processes and models together with de-embedding approaches are discussed and described. Then, a general design flow for a transformer-based matching network (TMN) is introduced to accelerate the design of multistage PAs. Further, two gain-boosting topologies are analyzed. The influence of capacitive gain-boosting on PA performance (maximum available power gain G-\{max\} , saturation power P-\{sat\} , drain efficiency DE and power-Added efficiency PAE) is studied for different silicon technologies after properly sizing the PA transistors to reach an optimum load resistance R-\{opt\}. The inductive gain-boosting PA is explored and compared with the capacitive gain-boosting one in SiGe BiCMOS to achieve an even higher P-\{sat\} while maintaining a high G-\{max\}. Finally, A D-band 4-stage capacitive gain-boosting PA is fabricated in a 28 nm bulk CMOS process as a reference to verify the design methodology and simulation results, and its detailed design considerations are described. This prototyped D-band PA achieved the state-of-The-Art results: A 22.5 dB G-\{p\} , 6.6 \% PAE, 8 dBm P-\{sat\} and 81.1 FoM with only 0.0265 mm2 core area.
Tang, X, Nguyen, J, Medra, A, Khalaf, K, Visweswaran, A, Debaillie, B & Wambacq, P 2020, 'Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies', IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 5, 9004504, pp. 1447-1458. https://doi.org/10.1109/TCSI.2020.2974197
Tang, X., Nguyen, J., Medra, A., Khalaf, K., Visweswaran, A., Debaillie, B., & Wambacq, P. (2020). Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(5), 1447-1458. Article 9004504. https://doi.org/10.1109/TCSI.2020.2974197
@article{18049c14faa14763817a516bed25e12f,
title = "Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies",
abstract = "This paper presents design considerations and methodology for D-band transformer-based Class-AB gain-boosting power amplifiers (PAs) in three advanced silicon technologies: 28 nm bulk CMOS (complementary metal oxide semiconductor), 22 nm FD-SOI (fully-depleted silicon on insulator), and 130 nm SiGe BiCMOS (Silicon-germanium bipolar-CMOS). Firstly, the choice of processes and models together with de-embedding approaches are discussed and described. Then, a general design flow for a transformer-based matching network (TMN) is introduced to accelerate the design of multistage PAs. Further, two gain-boosting topologies are analyzed. The influence of capacitive gain-boosting on PA performance (maximum available power gain G-\{max\} , saturation power P-\{sat\} , drain efficiency DE and power-Added efficiency PAE) is studied for different silicon technologies after properly sizing the PA transistors to reach an optimum load resistance R-\{opt\}. The inductive gain-boosting PA is explored and compared with the capacitive gain-boosting one in SiGe BiCMOS to achieve an even higher P-\{sat\} while maintaining a high G-\{max\}. Finally, A D-band 4-stage capacitive gain-boosting PA is fabricated in a 28 nm bulk CMOS process as a reference to verify the design methodology and simulation results, and its detailed design considerations are described. This prototyped D-band PA achieved the state-of-The-Art results: A 22.5 dB G-\{p\} , 6.6 \% PAE, 8 dBm P-\{sat\} and 81.1 FoM with only 0.0265 mm2 core area.",
author = "Xinyan Tang and Johan Nguyen and Alaaeldien Medra and Khaled Khalaf and Akshay Visweswaran and Bjorn Debaillie and Piet Wambacq",
note = "Funding Information: Manuscript received August 31, 2019; revised November 28, 2019 and February 4, 2020; accepted February 10, 2020. Date of publication February 20, 2020; date of current version May 1, 2020. This work was supported by the European Community{\textquoteright}s ECSEL Joint Undertaking under Grant 692477 (project REFERENCE) and Grant 737454 (project TARANTO). This article was recommended by Associate Editor B. Gosselin. (Xinyan Tang and Johan Nguyen contributed equally to this work.) (Corresponding author: Xinyan Tang.) Xinyan Tang, Johan Nguyen, and Piet Wambacq are with imec, 3001 Leu-ven, Belgium, and also with the Department of Electronics and Informatics (ETRO), Vrije Universiteit Brussel (VUB), 1050 Brussels, Belgium (e-mail: xinyan.tang@imec.be). Publisher Copyright: {\textcopyright} 2004-2012 IEEE. Copyright: Copyright 2021 Elsevier B.V., All rights reserved.",
year = "2020",
month = may,
doi = "10.1109/TCSI.2020.2974197",
language = "English",
volume = "67",
pages = "1447--1458",
journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "5",
}