Garcia Bardon, M., Sherazi, Y., Jang, D., Yakimets, D., Schuddinck, P., Baert, R., Mertens, H., Mattii, L., Parvais, B., Mocuta, A., & Verkest, D. (2018). Power-performance trade-offs for Lateral NanoSheets on ultra-scaled standard cells. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (pp. 143-144). Article 8510633 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510633

@inproceedings{5d968f2cf1f149a9b99b1903283436fa,
title = "Power-performance trade-offs for Lateral NanoSheets on ultra-scaled standard cells",
abstract = "In this paper, the performance of standard cells scaled down to 4.5 metal tracks based on Lateral NanoSheets is investigated for 3nm technology node targets using relevant logic benchmarks and power-aware metrics. The cell layout and parasitics in 4.5T cells set strong constraints on the NanoSheets geometry. The optimized NanoSheets could still outperform FinFETs by 9 to 20% frequency depending on circuit context, reaching 3nm node targets. An extra 21% performance improvement is expected with device level boosters enablement.",
author = "{Garcia Bardon}, M. and Y. Sherazi and D. Jang and D. Yakimets and P. Schuddinck and R. Baert and H. Mertens and L. Mattii and B. Parvais and A. Mocuta and D. Verkest",
year = "2018",
month = oct,
day = "25",
doi = "10.1109/VLSIT.2018.8510633",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "143--144",
booktitle = "2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018",
address = "United States",
note = "38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 ; Conference date: 18-06-2018 Through 22-06-2018",
}