Publication Details
Overview
 
 
Nereo Markulic, Nereo Markulic, Pratap Renukaswamy, Pratap Renukaswamy, Ewout Martens, Ewout Martens, Barend Van Liempd, Barend Van Liempd, Piet Wambacq, Piet Wambacq, Jan Craninckx, Jan Craninckx
 

Chapter in Book/ Report/ Conference proceeding

Abstract 

We present a subsampling polar transmitter (SSPTX) in 28nm CMOS that consists of a low-noise phase modulating (PM) digital subsampling PLL and a harmonic rejection mixed (HRM) inverse-class-D (D- 1 ) digital power amplifier (DPA) for amplitude modulation (AM). The DPA is, unlike in a typical polar TX, placed within the PLL and the phase-error detection happens directly at the DPA output. The subsampling polar TX thus becomes sensitive not only to phase-errors, but also to modulation amplitude. That feature enables AM distortion to be detected and canceled digitally in the background while the transmitter operates normally. The chip operates from a 0.9V supply at 5.5GHz with 2.5MHz BW and 1024 QAM, consuming on average 46mW.

Reference