Veloso, A., Matagne, P., Simoen, E., Kaczer, B., Eneman, G., Mertens, H., Yakimets, D., Parvais, B., & Mocuta, D. (2018). Junctionless versus inversion-mode lateral semiconductor nanowire transistors. Journal of Physics: Condensed Matter, 30(38), Article 384002. https://doi.org/10.1088/1361-648X/aad7c7

@article{77391321a9194fc38a1a26c9db25467a,
title = "Junctionless versus inversion-mode lateral semiconductor nanowire transistors",
abstract = "This paper reports on gate-all-around silicon nanowire field-effect transistors (FETs) built in a lateral configuration, which represent the ultimate scaling limit of triple-gate finFET devices and allow a less disruptive CMOS scaling path in terms of processing and circuit layout design. We address several of their critical technological challenges, looking in particular at doping strategies. A comprehensive review of junctionless versus inversion-mode type of transistors is here presented, evaluating the impact on the devices' operation mode and on device properties such as: variability, reliability, noise, DC and analog/RF performance. We also discuss the potential for further manufacturable co-integration options.",
keywords = "CMOS scaling, DC and analog/RF performance, junctionless and inversion-mode type of transistors, nanowire FETs, noise, reliability, variability",
author = "A. Veloso and P. Matagne and E. Simoen and B. Kaczer and G. Eneman and H. Mertens and D. Yakimets and B. Parvais and D. Mocuta",
year = "2018",
month = sep,
day = "3",
doi = "10.1088/1361-648X/aad7c7",
language = "English",
volume = "30",
journal = "Journal of Physics: Condensed Matter",
issn = "0953-8984",
publisher = "IOP Publishing",
number = "38",
}