Publication Details
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A. Vandooren, A. Vandooren, L. Witters, L. Witters, J. Franco, J. Franco, A. Mallik, A. Mallik, Bertrand Parvais, Bertrand Parvais, Z. Wu, Z. Wu, A. Walke, A. Walke, V. Deshpande, V. Deshpande, E. Rosseel, E. Rosseel, A. Hikavyy, A. Hikavyy, W. Li, W. Li, L. Peng, L. Peng, N. Rassoul, N. Rassoul, G. Jamieson, G. Jamieson, F. Inoue, F. Inoue, G. Verbinnen, G. Verbinnen, K. Devriendt, K. Devriendt, L. Teugels, L. Teugels, N. Heylen, N. Heylen, E. Vecchio, E. Vecchio, T. Zheng, T. Zheng, N. Waldron, N. Waldron, V. De Heyn, V. De Heyn, D. Mocuta, D. Mocuta, Nadine Collaert, Nadine Collaert
 

Chapter in Book/ Report/ Conference proceeding

Abstract ■

In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.

Reference ■
 
Vandooren, A, Witters, L, Franco, J, Mallik, A, Parvais, B, Wu, Z, Walke, A, Deshpande, V, Rosseel, E, Hikavyy, A, Li, W, Peng, L, Rassoul, N, Jamieson, G, Inoue, F, Verbinnen, G, Devriendt, K, Teugels, L, Heylen, N, Vecchio, E, Zheng, T, Waldron, N, De Heyn, V, Mocuta, D & Collaert, N 2018, Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling. in ICICDT 2018 - International Conference on IC Design and Technology, Proceedings. ICICDT 2018 - International Conference on IC Design and Technology, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 145-148, 2018 International Conference on IC Design and Technology, ICICDT 2018, Otranto, Italy, 4/06/18. https://doi.org/10.1109/ICICDT.2018.8399777
Vandooren, A., Witters, L., Franco, J., Mallik, A., Parvais, B., Wu, Z., Walke, A., Deshpande, V., Rosseel, E., Hikavyy, A., Li, W., Peng, L., Rassoul, N., Jamieson, G., Inoue, F., Verbinnen, G., Devriendt, K., Teugels, L., Heylen, N., ... Collaert, N. (2018). Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling. In ICICDT 2018 - International Conference on IC Design and Technology, Proceedings (pp. 145-148). (ICICDT 2018 - International Conference on IC Design and Technology, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICICDT.2018.8399777
@inproceedings{56f2854fef134f20927aecc724bc480c,
title = "Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling",
abstract = "In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.",
keywords = "3D sequential, junctionless, silicon-on-insulator, thermal budget, wafer bonding",
author = "A. Vandooren and L. Witters and J. Franco and A. Mallik and B. Parvais and Z. Wu and A. Walke and V. Deshpande and E. Rosseel and A. Hikavyy and W. Li and L. Peng and N. Rassoul and G. Jamieson and F. Inoue and G. Verbinnen and K. Devriendt and L. Teugels and N. Heylen and E. Vecchio and T. Zheng and N. Waldron and \{De Heyn\}, V. and D. Mocuta and N. Collaert",
year = "2018",
month = jun,
day = "27",
doi = "10.1109/ICICDT.2018.8399777",
language = "English",
isbn = "9781538625491",
series = "ICICDT 2018 - International Conference on IC Design and Technology, Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "145--148",
booktitle = "ICICDT 2018 - International Conference on IC Design and Technology, Proceedings",
address = "United States",
note = "2018 International Conference on IC Design and Technology, ICICDT 2018 ; Conference date: 04-06-2018 Through 06-06-2018",
}