The 60 GHz frequency synthesizer presented here demonstrates a transmitter error vector magnitude (EVM) between −28.8 and −26.5 dB, from 54 to 64.8 GHz, in 28 nm digital CMOS technology. This is suitable for IEEE 802.11-2016 communications with coded datarates up to 6.4 Gb/s. Its architecture, based on subharmonic injection locking, is immune to pulling by the power amplifier. A 24 GHz phase-locked loop, designed for low phase noise, locks a 60 GHz quadrature oscillator. The phase noise of the resulting 60 GHz carrier is between −96.5 and −93.8 dBc/Hz at 1 MHz offset. The frequency synthesizer, consuming 107 mW, is integrated and demonstrated with a 60 GHz transmitter front end.
Tsai, C-H, Mangraviti, G, Shi, Q, Khalaf, K, Bourdoux, A & Wambacq, P 2017, A 54-64.8 GHz Subharmonically Injection-Locked Frequency Synthesizer with Transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS. in 43rd European Solid-State Circuits Conference : ESSCIRC. IEEE, Leuven , pp. 243-246, 43rd European Solid-State Circuits Conference, Leuven, Belgium, 11/09/17. <http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8094571>
Tsai, C.-H., Mangraviti, G., Shi, Q., Khalaf, K., Bourdoux, A., & Wambacq, P. (2017). A 54-64.8 GHz Subharmonically Injection-Locked Frequency Synthesizer with Transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS. In 43rd European Solid-State Circuits Conference : ESSCIRC (pp. 243-246). IEEE. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8094571
@inproceedings{1eaaad4824d5410082a88664b3c28728,
title = "A 54-64.8 GHz Subharmonically Injection-Locked Frequency Synthesizer with Transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS",
abstract = "The 60 GHz frequency synthesizer presented here demonstrates a transmitter error vector magnitude (EVM) between −28.8 and −26.5 dB, from 54 to 64.8 GHz, in 28 nm digital CMOS technology. This is suitable for IEEE 802.11-2016 communications with coded datarates up to 6.4 Gb/s. Its architecture, based on subharmonic injection locking, is immune to pulling by the power amplifier. A 24 GHz phase-locked loop, designed for low phase noise, locks a 60 GHz quadrature oscillator. The phase noise of the resulting 60 GHz carrier is between −96.5 and −93.8 dBc/Hz at 1 MHz offset. The frequency synthesizer, consuming 107 mW, is integrated and demonstrated with a 60 GHz transmitter front end.",
author = "Cheng-Hsueh Tsai and Giovanni Mangraviti and Qixian Shi and Khaled Khalaf and Andr{\'e} Bourdoux and Piet Wambacq",
year = "2017",
language = "English",
pages = "243--246",
booktitle = "43rd European Solid-State Circuits Conference",
publisher = "IEEE",
note = "43rd European Solid-State Circuits Conference, ESSCIRC ; Conference date: 11-09-2017 Through 14-09-2017",
url = "https://www.esscirc-essderc2017.org/",
}