The two-point injection scheme has proven to be an effective technique for overcoming the problem of PLL bandwidth limitations during wideband polar phase modulation. The quality of the phase-modulated signal, typically expressed in terms of error-vector magnitude (EVM), still remains limited by the PLL phase-noise, gain mismatch between the two injection paths and linearity of the digital-to-modulated phase conversion. We present a phase modulator that makes use of an analog, fractional-N, digital-to-time-converter (DTC)-based subsampling PLL that achieves -37.4dB EVM around a 10.24GHz fractional carrier during 10Mb/s GMSK modulation. The subsampling PLL architecture uses no power-consuming divider and allows wide PLL bandwidth (because of its high phase-error detection gain) for optimal VCO noise suppression. The VCO has a secondary, digitally controlled capacitor bank (modulating DAC) used during two-point modulation. The gain errors and nonlinearities in the digital-to-modulated phase conversion are automatically background-calibrated in both injection points: in the phase-error detection path (where nonlinearity is dominated by the DTC INL) and in the VCO modulating capacitor bank (where nonlinearity is dominated by capacitor mismatch and nonlinear capacitance-to-frequency conversion).
Markulic, N, Raczkowski, K, Martens, E, Paro Filho, PE, Hershberg, B, Wambacq, P & Craninckx, J 2016, A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. in 2016 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, pp. 176-177, 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, United States, 31/01/16. https://doi.org/10.1109/ISSCC.2016.7417964
Markulic, N., Raczkowski, K., Martens, E., Paro Filho, P. E., Hershberg, B., Wambacq, P., & Craninckx, J. (2016). A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. In 2016 IEEE International Solid-State Circuits Conference (ISSCC) (pp. 176-177). IEEE. https://doi.org/10.1109/ISSCC.2016.7417964
@inproceedings{84dde80616ad4ce1b04c2d2ae754b7a5,
title = "A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL",
abstract = "The two-point injection scheme has proven to be an effective technique for overcoming the problem of PLL bandwidth limitations during wideband polar phase modulation. The quality of the phase-modulated signal, typically expressed in terms of error-vector magnitude (EVM), still remains limited by the PLL phase-noise, gain mismatch between the two injection paths and linearity of the digital-to-modulated phase conversion. We present a phase modulator that makes use of an analog, fractional-N, digital-to-time-converter (DTC)-based subsampling PLL that achieves -37.4dB EVM around a 10.24GHz fractional carrier during 10Mb/s GMSK modulation. The subsampling PLL architecture uses no power-consuming divider and allows wide PLL bandwidth (because of its high phase-error detection gain) for optimal VCO noise suppression. The VCO has a secondary, digitally controlled capacitor bank (modulating DAC) used during two-point modulation. The gain errors and nonlinearities in the digital-to-modulated phase conversion are automatically background-calibrated in both injection points: in the phase-error detection path (where nonlinearity is dominated by the DTC INL) and in the VCO modulating capacitor bank (where nonlinearity is dominated by capacitor mismatch and nonlinear capacitance-to-frequency conversion).",
author = "Nereo Markulic and Kuba Raczkowski and Ewout Martens and {Paro Filho}, {Pedro Emiliano} and Benjamin Hershberg and Piet Wambacq and Jan Craninckx",
year = "2016",
month = jan,
day = "31",
doi = "10.1109/ISSCC.2016.7417964",
language = "English",
isbn = "978-1-4673-9466-6",
pages = "176--177",
booktitle = "2016 IEEE International Solid-State Circuits Conference (ISSCC)",
publisher = "IEEE",
note = "2016 IEEE International Solid-State Circuits Conference (ISSCC) ; Conference date: 31-01-2016",
}