This paper presents a 10-bit, 550-fs step Digitalto-Time Converter (DTC) used in the phase comparison path of a fractional-N, TDC-less and divider-less PLL. The DTC is devised as a single-ended architecture which uses a tunable RC network for delay control. The circuit is optimized for low phase noise not to limit the in-band phase noise performance of the fabricated PLL. Measured INL and DNL are below 1.8 LSB and 0.8 LSB, respectively. The DTC phase noise floor is below -154 dBc/Hz at 0.5 mW power consumption from a 0.9 V supply. At 10 GHz output, the in-band phase noise of the PLL with the DTC embedded is -105 dBc/Hz. The PLL achieves 270 fs RMS jitter, consuming 26 mW.
Markulic, N, Raczkowski, K, Wambacq, P & Craninckx, J 2014, A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS. in P Andreani, A Bevilacqua & G Meneghesso (eds), ESSCIRC 2014 – 40th European Solid State Circuits Conference. IEEE, pp. 79-82, 40th European Solid‐State Circuit Conference, Venezia Lido, Italy, 22/09/14. https://doi.org/10.1109/ESSCIRC.2014.6942026
Markulic, N., Raczkowski, K., Wambacq, P., & Craninckx, J. (2014). A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS. In P. Andreani, A. Bevilacqua, & G. Meneghesso (Eds.), ESSCIRC 2014 – 40th European Solid State Circuits Conference (pp. 79-82). IEEE. https://doi.org/10.1109/ESSCIRC.2014.6942026
@inproceedings{6dca63c2801a45dc9e6b7b3cc06b0355,
title = "A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS",
abstract = "This paper presents a 10-bit, 550-fs step Digitalto-Time Converter (DTC) used in the phase comparison path of a fractional-N, TDC-less and divider-less PLL. The DTC is devised as a single-ended architecture which uses a tunable RC network for delay control. The circuit is optimized for low phase noise not to limit the in-band phase noise performance of the fabricated PLL. Measured INL and DNL are below 1.8 LSB and 0.8 LSB, respectively. The DTC phase noise floor is below -154 dBc/Hz at 0.5 mW power consumption from a 0.9 V supply. At 10 GHz output, the in-band phase noise of the PLL with the DTC embedded is -105 dBc/Hz. The PLL achieves 270 fs RMS jitter, consuming 26 mW.",
author = "Nereo Markulic and Kuba Raczkowski and Piet Wambacq and Jan Craninckx",
year = "2014",
month = sep,
day = "22",
doi = "10.1109/ESSCIRC.2014.6942026",
language = "English",
isbn = "978-1-4799-5694-4",
pages = "79--82",
editor = "Pietro Andreani and Andrea Bevilacqua and Gaudenzio Meneghesso",
booktitle = "ESSCIRC 2014 – 40th European Solid State Circuits Conference",
publisher = "IEEE",
note = "40th European Solid‐State Circuit Conference ; Conference date: 22-09-2014 Through 26-09-2014",
}