This paper presents a 79GHz fifth subharmonic injection locked oscillator (ILO). Compared to classical ILOs which are based on the nonlinearity of coupling transistors, this work uses inverter chains for input pulse pre-shaping. Thanks to the harmonic rich square wave, the new ILO combines linear and nonlinear mechanisms which together widen the locking range. A prototype chip is fabricated in 28nm CMOS technology. A locking range from 72 to 83GHz is measured under -2dBm input power. The power consumption of the inverter chain, the core circuit and the output buffer is 9mA, 10mA and 9mA respectively. Besides, a peak detector is implemented to ensure the locked ILO operates near the free-running frequency where the output amplitude is higher.
Shi, Q, Wambacq, P, Guermandi, D & Giannini, V 2014, A 5th subharmonic, inverter-based injection locked oscillator with 72–83GHz locking range. in Radio Frequency Integrated Circuits Symposium, 2014 IEEE., RMO3C-4, pp. 185-188, 2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Tampa, FL, United States, 1/06/14. https://doi.org/10.1109/RFIC.2014.6851692
Shi, Q., Wambacq, P., Guermandi, D., & Giannini, V. (2014). A 5th subharmonic, inverter-based injection locked oscillator with 72–83GHz locking range. In Radio Frequency Integrated Circuits Symposium, 2014 IEEE (pp. 185-188). Article RMO3C-4 https://doi.org/10.1109/RFIC.2014.6851692
@inproceedings{646bb88bf1f743e894d5bc36059a9290,
title = "A 5th subharmonic, inverter-based injection locked oscillator with 72–83GHz locking range",
abstract = "This paper presents a 79GHz fifth subharmonic injection locked oscillator (ILO). Compared to classical ILOs which are based on the nonlinearity of coupling transistors, this work uses inverter chains for input pulse pre-shaping. Thanks to the harmonic rich square wave, the new ILO combines linear and nonlinear mechanisms which together widen the locking range. A prototype chip is fabricated in 28nm CMOS technology. A locking range from 72 to 83GHz is measured under -2dBm input power. The power consumption of the inverter chain, the core circuit and the output buffer is 9mA, 10mA and 9mA respectively. Besides, a peak detector is implemented to ensure the locked ILO operates near the free-running frequency where the output amplitude is higher.",
author = "Qixian Shi and Piet Wambacq and Davide Guermandi and Vito Giannini",
year = "2014",
doi = "10.1109/RFIC.2014.6851692",
language = "English",
isbn = "978-1-4799-3862-9 ",
pages = "185--188",
booktitle = "Radio Frequency Integrated Circuits Symposium, 2014 IEEE",
note = "2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) ; Conference date: 01-06-2014 Through 03-06-2014",
}