A 60 GHz sub-sampling PLL implemented in 40 nm CMOS is presented in this paper. The sub-sampling phase detector (SSPD) runs at 30 GHz after an inductively-peaked static divide-by-two. Thanks to the lower frequency of operation, the effect of non-zero sampling aperture of the switch is minimized. A dummy divider of the quadrature PLL is utilized for the sub-sampling loop to avoid extra loading in the 60 GHz path. A 53.8-63.3 GHz QVCO uses super-harmonic coupling at 120 GHz for relaxed headroom at a 0.9 V supply and achieves a free-running phase noise down to -94.5 dBc/Hz at 1 MHz offset. The millimeter-wave sub-sampling PLL achieves an RMS jitter, integrated from 1 kHz to 100 MHz, of 200 fs at a power consumption of 42 mW, compared to 210 fs for the PFD/CP PLL at 75 mW. Reference spurs in both modes are below -40 dBc.
Szortyka, V, Shi, Q, Raczkowski, K, Parvais, B, Kuijk, M & Wambacq, P 2015, 'A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS', IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 50, no. 9, pp. 2025-2036. https://doi.org/10.1109/JSSC.2015.2442998
Szortyka, V., Shi, Q., Raczkowski, K., Parvais, B., Kuijk, M., & Wambacq, P. (2015). A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 50(9), 2025-2036. https://doi.org/10.1109/JSSC.2015.2442998
@article{23b71d3b1e6d4fc5917a833e90e5485e,
title = "A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS",
abstract = "A 60 GHz sub-sampling PLL implemented in 40 nm CMOS is presented in this paper. The sub-sampling phase detector (SSPD) runs at 30 GHz after an inductively-peaked static divide-by-two. Thanks to the lower frequency of operation, the effect of non-zero sampling aperture of the switch is minimized. A dummy divider of the quadrature PLL is utilized for the sub-sampling loop to avoid extra loading in the 60 GHz path. A 53.8-63.3 GHz QVCO uses super-harmonic coupling at 120 GHz for relaxed headroom at a 0.9 V supply and achieves a free-running phase noise down to -94.5 dBc/Hz at 1 MHz offset. The millimeter-wave sub-sampling PLL achieves an RMS jitter, integrated from 1 kHz to 100 MHz, of 200 fs at a power consumption of 42 mW, compared to 210 fs for the PFD/CP PLL at 75 mW. Reference spurs in both modes are below -40 dBc.",
author = "Viki Szortyka and Qixian Shi and Kuba Raczkowski and Bertrand Parvais and Maarten Kuijk and Piet Wambacq",
year = "2015",
month = jun,
day = "23",
doi = "10.1109/JSSC.2015.2442998",
language = "English",
volume = "50",
pages = "2025--2036",
journal = "IEEE JOURNAL OF SOLID-STATE CIRCUITS",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "9",
}