A 2.6 mW 6b 2.2GS/S 4-times Interleaved Fully Dynamic Pipelined ADC in 40 nm Digital CMOS

A 2.6 mW 6b 2.2GS/S 4-times Interleaved Fully Dynamic Pipelined ADC in 40 nm Digital CMOS ■

Bob Verbruggen, J. Craninckx, Maarten Kuijk, Piet Wambacq, G. Van Der Plas

Abstract ■

A 2.2 GS/S 4*-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. Threshold calibration corrects for amplifier and comparator imperfections and 31.6 dB SNDR is achieved with 2 GHz ERBW for 2.6 mW power consumption