Advanced process modules for (sub-) 45nm analog/RF CMOS - technology description and modeling challenges
 
Advanced process modules for (sub-) 45nm analog/RF CMOS - technology description and modeling challenges ■
 
S. Decoutere, V. Subramanian, J. Loo, C. Gustin, Bertrand Parvais, M. Dehan, A. Mercha
 
Abstract ■

The new process module and device architecture options emerging for (sub-) 45nm CMOS lead to both opportunities and challenges for Analog/RF circuit design. A survey will be given describing the advanced process modules for competing architectures (planar bulk CMOS versus FinFETS), for different gate stacks and mobility enhancement techniques. Challenges for compact modeling are identified.