Moore{\textquoteright}s law has for more than five decades been the roadmap guiding the semiconductor industry. While originally driven by lithography advancements and material innovation, since the 22 nm/14 nm node, new device architectures like FinFET have been introduced to tackle the increasing challenges related to power efficiency, performance, area scaling, and cost. With the introduction of FinFET, design-technology co-optimization also gained a lot of importance. More than ever, the industry is looking for that magic device concept to continue CMOS scaling beyond the 3 nm technology node. Gate-all-around devices, coming in different flavors (nanowires or nanosheets), have been proposed as possible candidates for keeping leakage under control. These architectures can be seen as an evolutionary step from FinFET. More disruptive is the introduction of high-mobility channel materials like (Si)Ge. While many hurdles have been overcome, especially the lower bandgap and thus higher leakage are still a concern. Next, going 3D seems a straightforward way to continue area scaling. Based on the gate-all-around integration scheme, complementary FET (CFET) where nMOS and pMOS are stacked on top of each other shows potential for not only area scaling but also power-performance improvements, but it comes at the cost of a more complex integration scheme. Finally, as the industry will move more toward heterogeneous integration, sequential 3D, allowing for fine-grained connections between the different layers of active devices, will be key in enabling these more complex systems.