A CMOS compatible III-v-on-300 mm SI technology for future high-speed communication systems: Challenges and possibilities

A CMOS compatible III-v-on-300 mm SI technology for future high-speed communication systems: Challenges and possibilities ■

Abhitosh Vais, Annie Kumar, Guillaume Boccardi, Sachin Yadav, Yves Mols, Reynald Alcotte, Bjorn Vermeersch, Marc Ingels, Uthayasankaran Peralagu, Cesar Roda Neve, Bruno Ghyselen, Bertrand Parvais, Piet Wambacq, Bernardette Kunert, Nadine Collaert

Abstract ■

III-V semiconductor-based devices, in particular InP heterojunction bipolar transistors, are a strong contender for next-generation high-speed communication systems. In this paper, we present motivation for the upscaling of III-V technology on to 300 mm Si platforms. A comparison of various options for such III-V on Si technology is described. The challenges in the way to achieve its integration into existing CMOS platform and possibilities to overcome them are shown. We describe imec's path to demonstrate a CMOS compatible III-V-on-300 mm Si technology with the most recent results.