Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling ■
A. Vandooren, L. Witters, J. Franco, A. Mallik,
Bertrand Parvais, Z. Wu, A. Walke, V. Deshpande, E. Rosseel, A. Hikavyy, W. Li, L. Peng, N. Rassoul, G. Jamieson, F. Inoue, G. Verbinnen, K. Devriendt, L. Teugels, N. Heylen, E. Vecchio, T. Zheng, N. Waldron, V. De Heyn, D. Mocuta,
Nadine CollaertIn this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.