Vertical device architecture for 5nm and beyond: device & circuit implications

Vertical device architecture for 5nm and beyond: device & circuit implications ■

AV-Y Thean, Dimitri Yakimets, Trong Huynh Bao, P. Schuddinck, Sushil Sakhare, M Garcia Bardon, A. Sibaja-Hernandez, I Ciofi, G. Eneman, A Veloso, Julien Ryckaert, Praveen Raghavan, A. Mercha, Z Tokei, Diederik Verkest, Piet Wambacq, Kurt De Meyer, Nadine Collaert

Abstract ■

Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.