A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS

A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS ■

Viki Szortyka, Qixian Shi, Kuba Raczkowski, Bertrand Parvais, Maarten Kuijk, Piet Wambacq

Abstract ■

this paper presents the first mm-Wave PLL utilizing a subsampling phase detector instead of a classical divider chain. Implemented in 40nm CMOS, the PLL has a jitter as low as 230fs for a power consumption of 42mW.